Simple ASIC Complex ASIC RaPiD FPGA GARP DPGA SuperSpeculative RAW TRACE ( Multiscalar ) SMT VECTOR

Poor scalability of Superscalar architectures with increasing instruction-level parallelism (ilp) has resulted in a trend towards statically scheduled horizontal architectures such as Very Large Instruction Word (vliw) processors and their more sophisticated successors called Explicitly Parallel Instruction Computing (epic) architectures. We extend the epic model with additional capabilities to reconngure the datapath at runtime in terms of the number and types of functional units comprising it. This yields a more general class of architectures which we call Adaptive Explicitly Parallel Instruction Computing (a-epic) architectures. We believe that these architectures are at the right level of granularity for automatic compilation (unlike many of the purely fpga based machines) and yet yield many of the performance beneets of reconngurable logic. We present the a-epic model and for an interesting subspace of a-epic architectures, the necessary compilation technology. We highlight many of the compilation problems associated with targeting reconngurable targets (of which a-epic's are part of) and show how they can be eeciently addressed within our framework. Performance results on a set media and signal processing applications are shown using our research compiler.